
	CPU	NS32016
	FPU	NS32081

	ORG	1000H

	MOVD	OPN,R1
	SVC
	DB	3		; STROUT


	SFSR	R0
	ANDD	0FFFFFFD7H,R0	; Clear IEN & UEN bit
	LFSR	R0
	
	MOVW	-12,R4		; Y
YLOOP:
	MOVWF	R4,F0
	MULF	0.08333,F0	; CB

	MOVW	-39,R5		; X
XLOOP:
	MOVWF	R5,F1
	MULF	0.0458,F1	; CA

	MOVF	F1,F2		; A = CA
	MOVF	F0,F3		; B = CB

	XORW	R6,R6		; I
ILOOP:
	MOVF	F2,F4
	MULF	F4,F4		; A*A

	MOVF	F3,F5
	MULF	F5,F5		; B*B

	SUBF	F5,F4
	ADDF	F1,F4		; T = A*A-B*B+CA

	MULF	F2,F3
	MULF	2.0,F3
	ADDF	F0,F3		; B = 2*A*B+CB

	MOVF	F4,F2		; A = T

	MOVF	F2,F4
	MULF	F4,F4		; A*A

	MOVF	F3,F5
	MULF	F5,F5		; B*B

	ADDF	F5,F4		; A*A+B*B

	CMPF	F4,4.0
	BLE	NEXT

	MOVB	R6,R0
	ADDB	'0',R0
	CMPB	'9'+1,R0
	BHI	SKIP
	ADDB	'A'-'9'-1,R0
SKIP:
	BR	BREAK

NEXT:
	ADDQW	1,R6
	CMPW	15+1,R6
	BHI	ILOOP

	MOVB	' ',R0
BREAK:
	SVC
	DB	2

	ADDQW	1,R5
	CMPW	39+1,R5
	BGT	XLOOP

	MOVB	0DH,R0
	SVC
	DB	2
	MOVB	0AH,R0
	SVC
	DB	2

	ADDQW	1,R4
	CMPW	12+1,R4
	BGT	YLOOP

	BPT

OPN:	DB	"ASCIIART",0DH,0AH,0
